LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;

entity FPGAtest is
	port(
		clk: in std_logic;
		output: out std_logic_vector(3 downto 0);
		transmit_error : out std_logic;
		transmit_valid :out std_logic
	);
end FPGAtest;

architecture shift of FPGAtest is
	--megafunction as a component
	component shiftreg
		PORT (
		clock		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		shiftout	: out std_logic;
		q			: out std_logic_vector(134 downto 0)
		);
	end component;
	--RAM Declaration as component
	component ram
		PORT
		(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
		);
	end component;
	--Begin
	signal address_ram : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
	signal send_enable : std_logic := '0';
	signal terr : std_logic := '0';
	signal transmit_valid_symbol : std_logic;
	begin


	mem : ram 
			port map (address=>address_ram, clock=>(not clk), wren =>'0', q=>  output, data=>"0000");

	process(clk)
		begin 
		if (clk'event and clk='0') then
			terr <= '0';
			address_ram <= address_ram + "00000001";
			if (address_ram > "10010000") then
				send_enable<='0';
			else
				send_enable<='1';
			end if;
		end if;
	end process;
		--process to determine output	
		
		transmit_error <= terr;
		transmit_valid <= send_enable;
		
end shift;